DisplayPort linkup issues

DisplayPort is a license and royalty-free standard designed to provide next-generation high-bandwidth for video and audio capability between video sources and destination sinks. Altera provides a DisplayPort IP MegaCore function which conforms to the Video Electronics Standards Association (VESA) specification version 1.2a. It supports a scalable main data link of 1, 2, or 4 differential data pairs (lanes) and bit rate of 1.62 / 2.7 / 5.4 Gbps per lane with an embedded clock.

While integrating the Altera DisplayPort IP MegaCore function (sink only) in an Arria V FPGA, we noticed intermittent link-up inconsistencies when connecting to different video sources (MacBook Pro, Linux machine, and Windows PC). Some of the link-up symptoms included long training sequences, source/sink lock-up, and incorrect source resolution detection. Initial development was done using Altera’s Quartus II version 13.1. After searching Altera’s Knowledge Base for “DisplayPort”, there were a number of issues reported that have been addressed in newer versions of the tools. Specifically, after migrating the DisplayPort design to Quartus II version 14.1, most of these issues were resolved.

Further details could be obtained at Altera IP Release Notes

42 comments on “DisplayPort linkup issues”

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