FPGA Design

Logic Crafters offers FPGA consulting/contracting services ranging from requirements gathering, detailed specification, custom IP for ASIC/FPGA designs, algorithm optimization, integration/verification and real-time emulation. We have experience with Altera and Xilinx devices. Our design methodology is simple, it consists of minimizing time in the lab by doing extensive functional simulations. This has consistently proven effective!
  • MatLab modeling (float & fixed-point)
  • Conversion of fixed-point models into cycle accurate RTL design(s) (Verilog & VHDL)
  • Custom test-bench generation and simulation (ModelSim)
  • Constraints generation (SDF) for physical design
  • Synthesis (Synplify Pro, Precision, and vendor-specific tools)
  • Place-and-route optimization techniques
  • Timing Closure (STA)
  • Real-time debugging (SignalTap, ChipScope)

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Some of our previous projects include:
  • DisplayPort, DDR3, PCIe, EMIF, TCL
  • FPGA (Xilinx Virtex-6) architecture/design and MATLAB modeling/verification of PSK spread-spectrum Modulators/De-modulators for secured radio communications. Tasks included RTL (VHDL) design of various signal-processing modules, test-bench generation, synthesis, and place-and-route optimization. Achieved first-pass HW verification success.
  • MPEG-4 micro-architecture of motion compensation and pre/post-processing image resize unit for wireless multimedia chip set. Designed/captured RTL (Verilog) of arithmetic logic, bi-linear interpolation, and memory controller sub-units. Experience in planning, executing, providing technical guidance, and tracking group tasks.
  • W-CDMA/GSM RTL (Verilog) design/implementation/integration of various modules including: delta-sigma fractional-N (synthesizer) accumulator system, frequency divider, SPI, and parallel test-bus interface. Performed system integration, mixed-signal simulations, code/test coverage, logic/physical synthesis, DFT/scan insertion, ATPG, static timing and power analysis, layout supervision, and parasitic-extracted simulations.
  • FPGA design/emulation using Xilinx devices and 3rd party evaluation boards for a two-way radio chip set. Performed audio filter measurements of integrated micro-controller (M-CORE) and signal processing IC. Developed PLI routines for DSP algorithm verification. Operational knowledge of digital test equipment.
  • Detailed ASIC design for arcade graphics processor and PC graphics accelerator chip set. Designed/implemented RTL (VHDL) of embedded floating-point RISC processor and state-machine control modules. Performed schematic capture, test vector generation, and behavioral/gate-level simulations. Knowledge of IEEE P754 standard.